Semiconductor memory device and method of operating the same

ABSTRACT

The present invention is directed to a semiconductor memory device and method of operating the same. In case where fail normal word lines of normal word lines from a normal memory block to which fail memory cells are connected is substituted by redundant word lines of a redundant memory block, the redundant word lines to replace the fail normal word lines are set in the redundant memory block. If the fail normal word lines are selected when the device is operated, the fail normal word lines and the redundant word lines are activated at the same time to increase capacitance of a capacitor connected to the sense amplifier. Therefore, it is possible to increase the exactness of a read operation or a refresh operation and improve reliability of a device operation, by increasing a comparable margin of the sense amplifier.

BACKGROUND

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory deviceand method of operating the same and, more particularly, to asemiconductor memory device and a method of operating the same, whichcan improve a refresh characteristic while replacing a fail word linewith a redundant word line.

[0003] 2. Discussion of Related Art

[0004] If even one of a large number of fine cells is defective, it doesnot properly serve as a memory and is treated as inferior goods.However, there is a high possibility that cell fail may take place inprobabilities as the level of integration in the memory is increased;even so, the fact that the entire memory cells must be discarded asinferior goods is an inefficient method to lower the yield (acquisitionratio of non-defective unit). In order to solve this problem, redundantmemory cells are deposited within the memory. The fail cell issubstituted by the redundant memory cell when the fail takes place inthe cell, thus improving the yield.

[0005]FIG. 1 shows a cell array structure of a semiconductor memorydevice having normal cells and redundancy cells.

[0006] Referring to FIG. 1, the memory device includes a normal memoryblock NMB having a plurality of normal word lines (for example, 256 innumber; NWL0 to NWL255 shown) for storing data, and a redundant memoryblock RMB having a plurality of redundant word lines (for example, 256in number; RWL0 to RWL255 shown) for substituting fail normal word linesof the normal memory block NMB.

[0007] After such a memory device is fabricated, whether a fail cell hasoccurred is finally checked through a test. If there is a fail cell (forexample, C100) of the memory cells included in the normal memory blockNMB, the fuse of the fuse ROM array (not shown) included in the memorydevice is cut to store address information (hereinafter referred to as‘fail address’) on a normal word line NWL0 to which the fail cell C100is connected. Such address information on the fail normal word line NWL0is compared with an external address (or internal address that isinternally generated for a refresh operation) externally inputted everytime when the memory device is operated. As a result of the comparison,if the fail address and the external address (or the internal address)are not coincident, it means that the normal word line (for example, oneof NWL1 to NWL255) does not have any fail cell. Therefore, acorresponding normal word line is selected and driven. If the failaddress and the external address (or the internal address) arecoincident, it means that the normal word line NWL0 has a fail cell.Accordingly, a signal inputted to the corresponding normal word lineNWL0 is applied to the redundant word line (for example, RWL0) of theredundant memory block RMB, thus driving the redundant word line RWL0.

[0008] Meanwhile, in the case of a memory cell having a singletransistor and a single capacitor, a data is stored at the capacitor. Inorder to increase the level of integration, the larger the size of thecapacitor, the faster the time where charges stored at the capacitor isdischarged. Thus, there is a difficulty in maintaining the data for anextended period of time. For this reason, in order to maintain the datastored for a long period of time, the memory cell performs a refreshoperation for restoring the data stored at the memory cell every giventime.

[0009] As such, in order to read the data stored at the memory cell aswell as the refresh operation, the redundant word line RWL0 to which thecorresponding memory cell (for example, C100) is connected is selectedand a voltage is detected through a bit line connected to the memorycell C100. At this time, in case where the memory cell C100 is a fail,as in the above, the redundant word line RWL0 is selected instead of thenormal word line NWL0 and the data is stored at the memory cell C110connected to the normal word line NWL0 and read therefrom. In the eventhat the data stored at the memory cell C110 connected to the normalword line NWL0 is read, a sense amplifier BLSA1 compares the voltagedetected through a bit line BL1 and a reference voltage (generally,Vcc/2) applied to an inverse bit line BL1# to read the data stored atthe memory cell C110.

[0010] If a data of ‘0’ is stored since charges are not stored at thecapacitor of the memory cell C110, it can be kept stably since there areno charges to be discharged. Further, the difference in the voltagebetween the bit line BL1 of 0 v and the inverse bit line BL1# of Vcc/2in the refresh or read operation is clearly distinguished, a read errorrarely takes place. In case where a data of ‘1’ is stored at thecapacitor of the memory cell C110 since the charges are stored at thecapacitor, it is impossible to keep stably the data of ‘1’ since thecharges are discharged as time goes. Therefore, in the refresh or readoperation, the sense amplifier BLSA1 must compare the difference in thevoltages (α) between the bit line BL1 of about α+Vcc/2 lower than Vccdue to the discharge and the inverse bit line BL1# of Vcc/2. As a resultof the comparison, if the difference in the voltage (α) is not so high,the read error may happen.

[0011] Furthermore, as the level of integration is increased, the lowercapacitance of the capacitor, the faster the speed that the chargesstored at the capacitor are discharged. For this reason, even if thefail word line is replaced with the redundant word line, it is notguaranteed that the data can be maintained stably. Further, the senseamplifier becomes more difficult to compare the difference in thevoltage between the bit line and the inverse bit line. There areproblems that the read error is increased and reliability of the deviceis lowered.

SUMMARY OF THE INVENTION

[0012] The present invention is directed to a semiconductor memorydevice and a method of operating the same, which can increase theexactness of a read operation or a refresh operation and improvingreliability of a device operation, by increasing a comparable margin ofa sense amplifier, in such a way that after redundant word lines toreplace fail normal word lines are set in a redundant memory block, thefail normal word lines and the redundant word lines are activated at thesame time to increase capacitance of a capacitor connected to the senseamplifier, if the fail normal word lines are selected when the device isoperated in case where the fail normal word lines from the normal wordlines of a normal memory block to which fail memory cells are connectedis substituted by the redundant word lines of the redundant memoryblock.

[0013] According to a preferred embodiment of the present invention,there is provided a semiconductor memory device, including a normal wordline block including a plurality of normal word lines to which memorycells are connected, a redundant word line block including a pluralityof redundant word lines for substituting fail normal word lines of theplurality of the normal word lines, to which fail memory cells areconnected, and a decoder for selecting one of the plurality of thenormal word lines according to an address signal, and selecting the failnormal word line and the redundant word line at the same time, if thefail normal word line is selected.

[0014] In the aforementioned of a semiconductor memory device accordingto another embodiment of the present invention, the decoder may includea X-address predecoder for selecting a memory block included in thenormal word line block or the redundant word line block according to theaddress signal, a row decoder and word line driver for selecting onenormal word line from the memory block regardless of whether the failmemory cell has been selected or not according to the address signal,and a redundant row decoder and word line driver for selecting theredundant word line corresponding to the fail normal word line accordingto the address signal if the fail normal word line of the plurality ofthe normal word line is selected.

[0015] In the aforementioned of a semiconductor memory device accordingto another embodiment of the present invention, the refresh circuit mayfurther include a bit line sense amplifier for reading data stored atthe memory cell connected to the normal word line or the redundant wordline, and wherein when the fail normal word line is selected, since thefail memory cell connected to the fail normal word line and theredundant memory cell connected to the redundant word line are connectedin parallel to one input terminal, both data stored at the fail memorycell and the redundant memory cell are read by the bit line senseamplifier.

[0016] In the aforementioned of a semiconductor memory device accordingto another embodiment of the present invention, the memory cell mayinclude a transistor having a gate connected to a word line and a drainconnected to a bit line, and a capacitor connected between a source ofthe transistor and the ground terminal.

[0017] In the aforementioned of a semiconductor memory device accordingto another embodiment of the present invention, the refresh circuit mayfurther include a repair address information storage means for storingaddress information on the fail normal word line to be repaired, towhich the fail memory cell is connected. At this time, the repairaddress information storage means may consist of a fuse ROM array havinga plurality of fuse ROMs.

[0018] In the aforementioned of a semiconductor memory device accordingto another embodiment of the present invention, the refresh circuit mayfurther include a comparator for comparing the address signal andaddress information on the fail normal word line and generating aredundant word line enable signal when the address signal and addressinformation are coincident, thus making the decoder select the redundantword line.

[0019] In the aforementioned of a semiconductor memory device accordingto another embodiment of the present invention, the address signalmentioned above is an external address inputted externally or aninternal address generated in a refresh counter for a refresh operation.

[0020] One aspect of the present invention is to provide a method ofoperating a semiconductor memory device, including the steps ofproviding a plurality of normal word lines to which a memory cell onwhich given data are stored is connected, and redundant word lines thatwill substitute fail normal word lines to which fail memory cells areconnected, storing address information on the fail normal word lines,inputting an address signal, comparing the address signal and addressinformation, if the address signal and address information are notcoincident, reading or refreshing the data stored at the memory cellconnected to the normal word lines, and if the address signal andaddress information are coincident, reading or refreshing the datastored at the fail memory cell connected to the fail normal word linesand the redundant memory cell connected to the redundant word lines, ina single sense amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 shows a cell array structure of a semiconductor memorydevice having normal cells and redundancy cells; and

[0022]FIG. 2 is a block diagram illustrating a semiconductor memorydevice according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0023] Now the preferred embodiments according to the present inventionwill be described with reference to the accompanying drawings. Sincepreferred embodiments are provided for the purpose that the ordinaryskilled in the art are able to understand the present invention, theymay be modified in various manners and the scope of the presentinvention is not limited by the preferred embodiments described later.

[0024]FIG. 2 is a block diagram illustrating a semiconductor memorydevice according to a preferred embodiment of the present invention.

[0025] In general, as the level of integration in the memory becomeshigher, a merged bank architecture (MBA) has been widely used wherein amemory is divided into a plurality of bank structures of over 4 banks,and all the banks share a X-address predecoder or a control block inorder to optimize the chip area. For easy understanding of the presentinvention, the bank structure will be described by way of an example.However, it is to be understood that the present invention is notrestricted to the bank structure.

[0026] Referring to FIG. 2, a core array 210 is a 1-bank structurehaving a plurality of memory blocks BK0 to BKn that are divided by two(upper and lower) bit line sense amplifiers BLSAs. Each of the memoryblocks BK0 to BKn has both a plurality of normal word lines NWL and aplurality of redundant word lines RWL.

[0027] A fuse ROM array 220 consists of a plurality of fuse ROMs (notshown) having the number corresponding to each of the plurality of thememory blocks BK0 to BKn. Address information on a fail normal word lineNWL that has to be repaired by a fail memory cell is programmed intoeach fuse ROM. At this time, address information on the fail normal wordline NWL that must be repaired may be stored using other informationstorage means other than the fuse ROM array 220.

[0028] A refresh counter 230 sequentially generates internal addressesat the time of a refresh operation.

[0029] A comparator 240 compares the external address and addressinformation programmed into the fuse ROM array 220 in the normaloperation, and compares address information programmed into the fuse ROMarray 220 and the internal address outputted from the refresh counter230 in the refresh operation. As a result of the comparison, if the twoaddresses are coincident, the comparator 240 activates a redundant wordline enable signal (RWEN). In other words, if the normal word line ofthe normal word lines NWL to which the fail memory cell is connected isselected in the normal operation or the refresh operation, thecomparator 240 activates the redundant word line enable signal (RWEN).

[0030] A decoder unit for selecting the word line may include aX-address predecoder 250, row decoder and word line drivers 260-1 to260-n, and redundant row decoder and word line drivers 261-1 to 261-n.

[0031] The X-address predecoder 250 decodes an external address(X-address) in the normal operation and decodes the internal addressoutputted from the refresh counter 230 in the refresh operation tooutput an upper coding signal being a memory block select signal and alower coding signal being a word line select signal. For example, in thecase of a 16M DRAM, the X-address predecoder 250 decodes addresses (A8to A11) of external addresses (A0 to A11) inputted thereto to select oneof the memory blocks BK0 to BKn. The addresses (A0 to A7) are used toselect one of the 256 word lines within one memory block, which areselected by the addresses (A8 to A11).

[0032] The row decoder and word line drivers 260-1 to 260-n enable thebit line sense amplifier BLSA according to the upper coding signaloutputted from the X-address predecoder 250 to select one of the memoryblocks BK0 to BKn. Further, the row decoder and word line drivers 260-1to 260-n select one of the normal word lines NWL within the blockselected by the upper coding signal without regard to whether the failnormal word line has taken place or not, according to the lower codingsignal outputted from the X-address predecoder 250.

[0033] The redundant row decoder and word line drivers 261-1 to 261-nare driven by the redundant word line enable signal (RWEN) outputtedfrom the comparator 240 to select one of the redundant word lines RWLwithin the block according to the lower coding signal outputted from theX-address predecoder 250.

[0034] In the prior art, at the time of the normal operation or therefresh operation, if a normal word line of the normal word lines NWL towhich the fail memory cell is connected is selected, the comparator 240activates only the redundant word line enable signal (RWEN) of thenormal word line enable signal (not shown) and the redundant word lineenable signal (RWEN) to operate only the redundant row decoder and wordline driver (any one of 261-1 to 261-n). In other words, the comparator240 controls the operation of the row decoder and word line drivers260-1 to 260-n depending on whether the fail normal word line has beenselected or not so that the fail normal word line is not selected.

[0035] In the present invention, however, the normal word line enablesignal is not generated in the comparator 240. Also even if a normalword line of the normal word lines NWL to which the fail memory cell isconnected is selected in the normal operation or the refresh operation,the row decoder and word line drivers 260-1 to 260-n stop operating, butoperates along with the redundant row decoder and word line drivers261-1 to 261-n.

[0036] For example, in a state where the normal word line enable signalthat had been inputted to the row decoder and word line drivers 260-1 to260-n is precluded in the comparator 240, if the row decoder and wordline drivers 260-1 to 260-n consist of NOR gates, a Vss voltage isapplied to the normal word line enable signal input terminal. If the rowdecoder and word line drivers 260-1 to 260-n consist of NAND gates, theVcc voltage is applied to the normal word line enable signal inputterminal. As the Vss voltage does not have any influence on the outputsignal of the NOR gate and the Vcc voltage does not have any influenceupon the output signal of the NAND gate, the row decoder and word linedrivers 260-1 to 260-n operate along with the redundant row decoder andword line drivers 261-1 to 261-n regardless of the normal word lineenable signal of the comparator 240.

[0037] As described above, if the row decoder and word line drivers260-1 to 260-n and the redundant row decoder and word line drivers 261-1to 261-n operate at the same time, a normal word line (for example,NWL0) to which a fail memory cell (for example, C100) is connected and aredundant word line (for example, RWL0) for substituting the normal wordline are selected at the same time, as shown in FIG. 1. As a result, asthe fail memory cell C100 and the redundant memory cell C110 areconnected in parallel to one of the input terminals of the bit linesense amplifier BLSA1, the capacitor of the fail memory cell and thecapacitor of the redundant memory cell are also connected in parallel.Therefore, capacitance of the capacitor connected to the input terminalof the bit line sense amplifier BLSA is increased. A comparable marginof the sense amplifier BLSA1 is thus increased to increase the exactnessof the read operation or the refresh operation and improve reliabilityof the device operation.

[0038] The operation of the refresh circuit of the semiconductor memorydevice constructed above will be described in more detail.

[0039] 1 In Case of Normal Operation

[0040] First, a given data is stored at the memory cell connected to theplurality of the normal word lines, address information on the failnormal word line to which the fail memory cell is connected is stored,and the redundant word line for substituting the fail normal word lineis specified.

[0041] Thereafter, if the external address is inputted, the X-addresspredecoder 250 decodes the external address (X-address) to output theupper coding signal and the lower coding signal. Further, the comparator240 sequentially compares the inputted external address and addressinformation programmed into the fuse ROM array 220. As a result of thecomparison, if the two addresses are coincident, the comparator 240activates the redundant word line enable signal (RWEN).

[0042] If the external address and address information programmed intothe fuse ROM array 220 are not coincident, the redundant word lineenable signal (RWEN) is not activated. Thus, the redundant row decoderand word line drivers 261-1 to 261-n do not operate but only theplurality of the row decoder and word line drivers 260-1 to 260-nnormally operate. Each of the row decoder and word line drivers 260-1 to260-n enables a corresponding bit line sense amplifier BLSA according tothe upper coding signal outputted from the X-address predecoder 250 toselect one of the plurality of the memory blocks BK0 to BKn (forexample, memory block BK0). At the same time, the row decoder and wordline drivers 260-1 to 260-n select and drive one of he normal word linesNWL within the memory block BK0 according to the lower coding signaloutputted from the X-address predecoder 250.

[0043] Meanwhile, if the external address and address informationprogrammed into the fuse ROM array 220 are coincident, the comparator240 activates the redundant word line enable signal (RWEN). For thisreason, the redundant row decoder and word line driver 261-1 is enabledto operate. At this time, the row decoder and word line driver 260-1normally operates regardless of whether the addresses are coincident ornot. In other words, although the fail normal word line to which thefail memory cell is connected is selected, the row decoder and word linedriver 260-1 normally operates. Therefore, the row decoder and word linedriver 260-1 selects and drives the normal word lines NWL within thememory block BK0 according to the lower coding signal outputted from theX-address predecoder 250. In addition, the redundant row decoder andword line driver 261-1 selects and operates the redundant word lines RWLwithin the memory block BK0 according to the lower coding signaloutputted from the X-address predecoder 250.

[0044] As described above, if the external address and addressinformation programmed into the fuse ROM array 220 are not coincident,only the normal word lines NWL are driven. If the two addresses arecoincident, the redundant word line enable signal (RWEN) is activatedand the normal word lines NWL and the redundant word lines RWL to whichthe fail memory cell is connected are thus driven at the same time.

[0045] Through the above operation, if the fail memory cell and theredundant memory cell are connected in parallel to one of the inputterminals of the bit line sense amplifier BLSA, the capacitor of thefail memory cell and the capacitor of the redundant memory cell are alsoconnected in parallel. Capacitance of the capacitor connected to theinput terminal of the bit line sense amplifier BLSA is increasedaccordingly. The comparable margin of the sense amplifier BLSA1 is thusincreased to increase the exactness of the read operation or the refreshoperation and improve reliability of the device operation.

[0046] 2. In Case of the Refresh Operation

[0047] The refresh counter 230 sequentially generates the internaladdresses, according to the refresh command, to provide them to thecomparator 240. The X-address predecoder 250 decodes the internaladdresses outputted from the refresh counter 230 to output the uppercoding signal and the lower coding signal.

[0048] At this time, the comparator 240 sequentially compares theinputted internal addresses and address information programmed into thefuse ROM array 220. As a result of the comparison, if the two addressesare coincident, the comparator 240 activates the redundant word lineenable signal (RWEN).

[0049] And, the X-address predecoder 250 decodes the internal addressinputted from the refresh counter 230 to output the upper coding signaland the lower coding signal. The plurality of the row decoder and wordline drivers 260-1 t 260-n select one of the plurality of the memoryblocks BK0 to BKn according to the lower coding signal outputted fromthe X-address predecoder 250. The plurality of the row decoder and wordline drivers 260-1 to 260-n sequentially operate the normal word linesNWL according to the lower coding signal within the selected memoryblocks to perform the refresh operation.

[0050] In addition, the redundant row decoder and word line driver 261-1is enabled by the redundant word line enable signal (RWEN) and thusdrives the redundant word lines RWL within the selected memory blockaccording to the lower coding signal outputted from the X-addresspredecoder 250 to perform the refresh operation.

[0051] In other words, if the internal address and address informationprogrammed into the fuse ROM array 220 are not coincident even upon therefresh operation, the redundant row decoder and word line driver 261-1drives the normal word lines NWL to perform the refresh operation. Ifthe two addresses are coincident, the redundant row decoder and wordline driver 261-1 drives the normal word lines NWL and the redundantword lines RWL using the redundant word line enable signal (RWEN), thusperforming the refresh operation.

[0052] As in the above, the method of driving the normal word line andthe redundant word line at the same time can be applied to where thenormal word line and the redundant word line do not exist within thesame memory block. In other words, since the normal word line and theredundant word line are selected by different decoders, it is onlynecessary to drive the decoder that selects the normal word line and thedecoder that selects the redundant word line are driven at the sametime, when the normal word line to which the fail memory cell isconnected is selected.

[0053] According to the present invention, if a normal word line towhich a fail memory cell is connected is selected, a normal word lineand a redundant word line for substituting the normal word line aredriven at the same time to increase capacitance of a capacitor connectedto a sense amplifier. Therefore, it is possible to increase a comparablemargin of the sense amplifier, thus increasing the exactness of a readoperation or a refresh operation and improving reliability of a deviceoperation.

[0054] Although the foregoing description has been made with referenceto the preferred embodiments, it is to be understood that changes andmodifications of the present invention may be made by the ordinaryskilled in the art without departing from the spirit and scope of thepresent invention and appended claims.

What is claimed is:
 1. A semiconductor memory device comprising: anormal word line block including a plurality of normal word lines towhich memory cells are connected; a redundant word line block includinga plurality of redundant word lines for substituting fail normal wordlines, to which fail memory cells are connected, of the plurality of thenormal word lines; and a decoder for selecting one of the plurality ofthe normal word lines according to an address signal, and selecting thefail normal word line and the redundant word line at the same time, ifthe fail normal word line is selected.
 2. The semiconductor memorydevice as claimed in claim 1, wherein the decoder comprises: a X-addresspredecoder for selecting a memory block included in the normal word lineblock or the redundant word line block according to the address signal;a row decoder and a word line driver for selecting one normal word linefrom the memory block regardless of whether the fail memory cell hasbeen selected or not according to the address signal; and a redundantrow decoder and a word line driver for selecting the redundant word linecorresponding to the fail normal word line if the fail normal word lineof the plurality of the normal word line is selected according to theaddress signal.
 3. The semiconductor memory device as claimed in any oneof claims 2, wherein the address signal is an external address inputtedexternally or an internal address generated in a refresh counter for arefresh operation.
 4. The semiconductor memory device as claimed inclaim 1, further comprising a bit line sense amplifier for reading datastored at the memory cell connected to the normal word line or theredundant word line and, when the fail normal word line is selected,since the fail memory cell connected to the fail normal word line andthe redundant memory cell connected to the redundant word line areconnected in parallel to one input terminal, both data stored at thefail memory cell and the redundant memory cell are read by the bit linesense amplifier.
 5. The semiconductor memory device as claimed in claim4, wherein the memory cell comprises: a transistor having a gateconnected to a word line and a drain connected to a bit line; and acapacitor connected between a source of the transistor and the groundterminal.
 6. The semiconductor memory device as claimed in claim 1,wherein the memory cell comprises: a transistor having a gate connectedto a word line and a drain connected to a bit line; and a capacitorconnected between a source of the transistor and the ground terminal. 7.The semiconductor memory device as claimed in claim 1, furthercomprising a repair address information storage mean for storing addressinformation on the fail normal word line to be repaired, to which thefail memory cell is connected.
 8. The semiconductor memory device asclaimed in claim 7, wherein the repair address information storage meanconsists of a fuse ROM array having a plurality of fuse ROMs.
 9. Thesemiconductor memory device as claimed in claim 1, further comprising acomparator for comparing the address signal and address information onthe fail normal word line and generating a redundant word line enablesignal when the address signal and address information are coincident,thus making the decoder select the redundant word line.
 10. Thesemiconductor memory device as claimed in any one of claims 9, whereinthe address signal is an external address inputted externally or aninternal address generated in a refresh counter for a refresh operation.11. The semiconductor memory device as claimed in any one of claims 1,wherein the address signal is an external address inputted externally oran internal address generated in a refresh counter for a refreshoperation.
 12. A method of operating a semiconductor memory device,comprising the steps of: providing a plurality of normal word lines towhich a memory cell, in which given data are stored, is connected, andredundant word lines that will substitute fail normal word lines towhich fail memory cells are connected; storing address information onthe fail normal word lines; inputting an address signal; comparing theaddress signal and address information; if the address signal andaddress information are not coincident, reading or refreshing the datastored at the memory cell connected to the normal word lines; and if theaddress signal and address information are coincident, reading orrefreshing the data stored at the fail memory cell connected to the failnormal word lines and the redundant memory cell connected to theredundant word lines, in a single sense amplifier.